When an integrated circuit is powered up, there exists the possibility of state conflicts and/or contention. Such events can cause opposing complimentary devices on the same circuit nodes (i.e., an NMOS pull-down transistor and a PMOS pull-up transistor) to be simultaneously conducting, resulting in a short-circuit current between V.sub.DD and V.sub.SS. Many parallel conflicts can be present causing an excessively large short-circuit current, potentially damaging or stressing the on-die metal power routing and/or the system power supply. In portable applications, where the power supply is a battery, this can be a critical problem that curtails battery life. Furthermore, in some portable applications, power-supply cycling is used to extend battery life (i.e., during lulls in processing, the power supply is turned off to the microprocessor). Thus, the power supply is turned off and on repeatedly, further exacerbating the above problems.
One prior method addressing the above problems is the use of a global asynchronous reset signal. The reset signal is used to initialize all required circuit nodes such that state conflicts and contention are eliminated. This requires at least one extra device at each requisite node and the presence of the reset signal. Given the complexity of a microprocessor, the number of nodes requiring initialization can be very large. Thus, the global reset distribution (metal) can be exceedingly large as can the number of extra devices (transistors) necessary to implement the reset function. This adversely impacts the size, cost, and power consumption of the integrated circuit.
Another method addressing the above problems is to require that the external and internal clocks be running during power-up. This allows reset processing to take place while power ramps up thereby initializing the requisite nodes and eliminating state conflicts and contention. This method is often impractical (or impossible) for the system designer who must ensure a valid clock before the power supply has reached its valid level. Since internal clocks are running throughout the power-supply ramp and until normal processing commences, power (CV.sup.2 F) is being wasted. This is also counter to the trend towards portable applications where it is important to reduce power and use power management techniques to extend battery life. Should a system design use power cycling as the primary power-management technique, the problem is further exacerbated. Phase-locked loops (PLLs) pose another drawback to this technique. PLL-based internal clocks have an indeterminate frequency and phase (to a reference clock) at power up; therefore, reset processing can not be ensured until after phase lock and phase lock can not be assured until after the power supply is at the specified level. During the phase-lock interval, excess power is still consumed due to contention or state conflicts.